Table of Content (toc)
1. When the value 37H is divide by 17H, the remainder is
-
C0 H
03 H
07 H
2. If negative numbers are stored in 2's complemented form, the range of numbers that can be stored in 8 bits is
-
-128 to-128
-128 to 127
-127 to-128
3. The addressing mode used in an instruction of the form ADD X, Y, is
-
Absolute
Immediate
Indirect
4. A combinational logic circuit which sends data coming from a single source to twoor more separate destinations is
- Decoder.
Encoder.
Multiplexer.
5. The three main components of a digital computer system are
-
Memory, IO, DMA
ALU, CPU, Memory
CPU, Memory, 10
6. The performance of cache memory is frequently measured in terms of a quantity called
- Miss ratio.
Hit ratio.
Latency ratio.
7. A Stack-organised Computer uses instruction of
-
Indirect addressing
Two-addressing
Zero addressing
8. The cost of storing a bit is minimum in
-
Cache memory
Register
RAM
9. The functional capacity of SSI devices is
-
1-11 gates
12 to 99 gates
100 to 10,000 gates
10. The idea of cache memory is based ______.
-
on the property of locality of reference
on the heuristic 90-10 rule
on the fact that references generally tend to cluster
11. Which of the following statement(s) is true?
-
ROM is a read/write memory
PC points to the last instruction that was executed
Stack works on the principle of LIFO
12. What characteristic of RAM memory makes it not suitable for permanentstorage?
-
too slow
unreliable
it is volatile
13. A resolution of _____ pixels will produce sharper image than 640 x 480 pixels.
-
800 x 600
1024 x 800
1024 x 640
14. Tera is 2 to the power of
-
9
15. ___ units are generally floating-point units that are completely pipelined.
-
Scalar registers
Vector load and store unit
Vector functional unit
16. 2n-1 is the largest integer in 2's complement representation using n bits.
10 The least negative value that the product of two 8-bit two's complement numbers can take is
-
-214
-215
-210
17. In immediate addressing the operand is placed
-
in the CPU register
after OP code in the instruction
in memory
18. Data input command is just the opposite of a
-
Test command
Control command
Data output
19. PSW is saved in stack when there is a _____.
-
interrupt recognized
execution of RST instruction
Execution of CALL instruction
20. In register addressing mode operands are looked at
-
In cache
In secondary storage
In CPU
21. Computers use addressing mode techniques for ____________.
-
giving programming versatility to the user by providing facilities as pointers to memory counters for loop control
to reduce no. of bits in the field of instruction
specifying rules for modifying or interpreting address field of the instruction
22. The shift left and shift right functions operate on the value in the
-
ACCUM
AREG
BASIC
23. Which of the following comment about the program counter is true?
-
It is used to count the no. of instructions
It is a cell in ROM
During execution of the current instruction, its content changes
24. ___ is an operation that fetches the non-zero elements of a sparse vector from memory.
-
Strip mining
ETA-10
Scatter
25. The master indicates that the address is loaded onto the BUS, by activating signal.
-
MSYN
SSYN
WMFC
26. The numbers in the range -23 to +31 is represented by the minimum number of bits :
27. The speed imbalance between memory access & CPU operation can be reduced by -
28. The sequence of events that happen during a typical fetch operation is
-
PC MDR-Memory →IR
PC-MAR-Memory-MDR→IR
PC Memory-IR
29. The circuit converting binary data in to decimal is_____.
-
Encoder
Multiplexer
Decoder
30. BCD stands for
-
Boolean code definition
Binary coded division
Binary coded decimal
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