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Computer Organization & Architecture MCQ [ Set - 19 ] | Computer Organization and Architecture Mcq with Answers

 

Computer Organization and Architecture Mcq with Answers

Table of Content (toc)



1. 15. An SIMD computer exploits ___ parallelism-

     Spatial
    Temporal
    Both a & b
ANSWER= (A) Spatial

 

2. The ‘T’ in the flip flop stands for ……………………..

    Time
     Transfer
    Toggle
ANSWER= (C) Toggle

 

3. The average time required to reach a storage location in memory and obtainits contents is called the _____.

    seek time
    turnaround time
     access time
ANSWER= (C) access time

 

4. The circuit used to store one bit of data is known as_______.

    Register
    Encoder
    Decoder
ANSWER= (D) Flip Flop

 

5.  ___ the pipeline solution is considered attractive due to its simplicity for hardware and software.

    Instruction count – 0xFF01
    Flush
    Load-stall count – 0xFF02

ANSWER= (B) Flush

 

6. Negative numbers cannot be represented in 

     Sign-magnitude form
    1's complemented form 
    2's complement form
ANSWER= (D) none of the above.

 

7. Associate memory can be used to build ___ associative processors.

    SISD
    SIMD
     MISD
ANSWER= (B) SIMD

 

8. If a processor does not have any stack pointer register, then

     It cannot have subroutine call instruction
     It can have subroutine call instruction, but no nested subroutine
     Nested subroutine calls are possible, but interrupts are not
ANSWER= (D)  All sequences of subroutine calls and also interrupts are

 

9. The addressing mode used in an instruction of the form ADD X.Y is

    absolute register
    immediate
    indirect 
ANSWER= (D)  index

 

10. The example of implied addressing is

    Stack addressing
     Immediate addressing
     Indirect addressing
ANSWER= (A) Stack addressing

 

11. In which addressing mode the operand is given explicitly in the instruction

    Absolute.
    Immediate .
     Indirect.
ANSWER= (B)  Immediate .

 

12.Any instruction should have at least

    3 operands
     2 operands
    1 operand
ANSWER= (D) none of the above

 

13. A three input NOR gate gives logic high output only when_____.

    one input is high
     one input is low
     two input are low
ANSWER= (D) all input are high

 

14. In a half – adder, CARRY is obtained by using

    OR gate
    NAND gate
    AND gate
ANSWER= (D) AND gate

 

15.  Which of the following rule(s) regarding the addition of 2 given numbers in 2's complement is correct.

    Add sign bit and discard carry, if any
    Add sign bit and add carry, if any 
    don't Add sign bit and discard carry, if any
ANSWER= (A) Add sign bit and discard carry, if any

 

16. Using Binary division, divide 1011011 by 111

    101.01
     1011
     011.01
ANSWER= (B) 1011

 

17. (2FAOC)16 is equivalent to _____.

    (195 084)10
    (001011111010 0000 1100)2
    Both A.and (B)
ANSWER= (B) (001011111010 0000 1100)2

 

18. (2FAOC)16 is equivalent to _____.

     (195 084)10
    (001011111010 0000 1100)2
    Both A.and (B)
ANSWER= (B) (001011111010 0000 1100)2

 

19. The ALU performs the indicated operation on the operands prepared in the prior cycle and store the result in the specified destination operand location.

    Fetch instruction
     Decode instruction
    Execute instruction
ANSWER= (C) Execute instruction

 

20. The exponent of a floating point number is represented in excess-N code (biased) so that

     the dynamic range is large
    the precision is high
    the smallest number is represented by all zeroes 
ANSWER= (A) the smallest number is represented by all zeroes 

 

21. There are ___ families of pipelined vector processors.





ANSWER= (A) 2

 

22.  The ___ architecture of a processor often referred to as simply the architecture of the processor.

    Abstract
     Concrete
    Encapsulated
ANSWER= (A) Abstract

 

23. If negative numbers are stored in 2's complemented form, the range of numbers that can stored in 8 bits is

    -128 to +128 
    -128 to +127
    -127 to +128 
ANSWER= (B) -128 to +127

 

24.  ___ Architecture supports the pipelined flow of vector operands directly from the memory to Pipelines and then back to the memory. ___ Architecture uses vector registers to interface between the memory and functional Pipelines.

     Memory –to-register, Register – to – Register
    Memory –to-Memory, Register – to – Register
    Memory –to-Pipelines, Register – to – Memory
ANSWER= (B) Memory –to-Memory, Register – to – Register

 

25.Which of the architecture is power efficient?

    CISC
    RISC
     ISA
ANSWER= (B) RISC

 

26. The largest integer that can be represented in signed-2's complement representation using n bits is

     2n-1
    2n
    2n-1-1
ANSWER= (D) 2n-1

 

27. A stack organized computer has

    Three-address Instruction.
    Two-address Instruction.
    One-address Instruction.
ANSWER= (D) Zero-address Instruction.

 

28. The three main components of a digital computer system are

     Memory, 10, DMA 
     ALU.CPU,Memory
    CPU, Memory, 10.
ANSWER= (D) Control Unit, ALU,Register.

 

29.  If the radix point (binary point) is fixed and assumed to be on the right of the rightmost digit, the representation of such a number is called

    Fixed point
    Floating point
    Radix point
ANSWER= (A) Fixed point

 

30. _________ register keeps tracks of the instructions stored in program storedin memory.

     AR (Address Register)
    XR (Index Register)
    PC (Program Counter)
ANSWER= (C) PC (Program Counter)




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