Table of Content (toc)
1. Cache memory is
-
volatile
both of the above
not known
2. A register capable of shifting its binary information either to the right or the left is called a
-
parallel register.
serial register.
shift register.
3. What is the content of Stack Pointer (SP)?
-
Address of the current instruction
Address of the next instruction
Address of the top element of the stack
4. Random access means
-
time to access any record is same
time to access a record may be anything.
time to access a record depends on the position of the record
5. The method of writing symbol to indicate a provided computational process is called as a:
- Programming language
Random transfer language
Register transfer language
6. In magnetic tape accessing mode is
-
random
sequential
both
7.Which operations are used for addition, subtraction, increment, decrement and complement function:
-
Bus
Memory transfer
Arithmetic operation
8. In ROM, assessing technique is
-
random
sequential
both sequential and random
9. Von Neumann architecture is
-
SISD
SIMD
MIMD
10. ___ Model is more suitable for special purpose computations.
-
SIMD
MISD
MIMD
11.In comparison to general main memory, cache memory is
-
faster
cheaper
longer
12. In a vectored interrupt.
-
the branch address is assigned to a fixed location in memory.
the interrupting source supplies the branch information to the processor through an interrupt vector.
the branch address is obtained from a register in the processor
13. Hazards in pipelines can make it necessary to ___ the pipeline.
-
Stall
Stake
Storm
14. Which of the following comment about the program counter is true?
-
It is used to count the no of instructions
It is a cell in ROM
During execution of the current instruction, its content changes
15.Which specific task is not included in superscalar processing?
-
Parallel decoding
Superscalar instruction
Parallel instruction
16. In register transfer the processor register as:
-
MAR
PC
IR
17. The speed imbalance between memory access & CPU operation can be reduced by -
-
Cache memory
memory interleaving
reducing memory size
18. ___ processors have fewer and simpler instructions than CISC processors.
-
GPR, RISC
RISC, GPR
CPU, CISC
19. The cost of storing a bit is minimum in -
-
Cache memory
Register
RAM
20. The system bus is made up of
-
data bus
data bus and address bus
data bus and control bus
21. BCD stands for
-
Boolean code definition
Binary coded division
Binary coded decimal
22. Which of the following statement(s) is true?
-
ROM is a read/write memory
PC points to the last instruction that was executed
Stack works on the principle of LIFO
23. An adder-subtractor single unit can be designed using full adder and
-
OR gates
XOR gates
NOR gates
24. Which of the following is not involved in a memory write operation?
-
MAR
PC
MDR
25. Tera is 2 to the power of -
26. A system which has lot crashes, data should be written to be disk using
-
write-through
write-back
both of the above
27. An 8-bit binary word b7b6b5b4b3b2b1b0 as an integer x ranges from
-
-128 to 128
-128 to 127
-256 to 256
28. The difference between memory and storage is that memory is and storage is
-
Temporary, permanent
Permanent, temporary
Slow, fast
29. The cost of a parallel processing is primarily determined by :
-
Time Complexity
Switching Complexity
Circuit Complexity
30. A repository for data, usually covering specific topic is
-
Database
Data collection
Data requisition
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