Table of Content (toc)
1. The less space consideration as lead to the development of (for large memories).
2. Polled intrrupet are handled by
-
software
hardware
firmware
3. Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then the refresh overhead of the chip is
-
0.0021
0.0038
0.0064
4. The half adder performs
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Decimal addition operation for 2 decimal inputs
Binary addition operation for 2 binary inputs
Decimal addition operation for 2 binary inputs
5. (2FAOC)16
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(195084)10
(00101111101000001100)2
Both (a) and (b)
6. In a normal n-bit adder, to find out if an overflow has occurred, we make use of
-
AND gate
NAND gate
NOR gate
7. A Flip-Flop circuit can be used for
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Counting
Scaling
Rectification
8. Given a 5 stage pipeline with stages taking 1,2,3,1, 1 units of time, the clock period of the pipeline is
1/8
1/3
9. A 32-bit address bus allows access to a memory of capacity
-
64 Mb
16 Mb
1 Gb
10. Which of the following data transfer mode takes relatively more time?
-
DMA
interrtupt initiated I/O
programmed I/O
11. Which of the following shift operations divide a signed binary number by 2 ?
-
Logical left shift
Logical right shift
Arithmetic left shift
12. For which of the following multiplier numbers in Booth's algorithm maximum no. of additions and subtractions are required?
-
01001111
01111000
00001111
13. Which of the following holds data and processing instructions temporarily unit the CPU needs it?
-
ROM
control unit
main memory
14. Octal equivalent of hexadecimal code, F3A1 is
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173101
176541
171641
15. The resolution of the D/A converter is approximately 0.4% of its full-scale range. It is a
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8 – bit converter
10 – bit converter
12– bit converter
16. The operation which is cumulative but not associative is
-
AND
OR
EX-OR
17. The dual of the boolean theorm A.(B+C) = A.B + A.C is
-
A + (B+C) = A.B + A.C
A.(B+C) = (A+B) + (A+C)
A+B.C = (A+B) + (A+C)
18. Which is true
A. For the pipelines – when an instruction is installed, all instructions issued.
B. Hazards in the pipelines can make it necessary to stall the pipelines
C. New instructions are fetched during the stall
D. Control Hazards can cause a greater performance loss than the data hazards
-
A & B
A, C, & D only
A, B & D Only
19. Generally Dynamic RAM is used as main memory in a computer system asit______.
-
Consumes less power
has higher speed
has lower cell density
20. Write Through technique is used in which memory for updating the data_____.
-
Virtual memory
Main memory
Auxiliary memory
21. Cache memory acts between_______.
22. SIMD represents an organization that
-
refers to a computer system capable of processing several programs at the same time.
represents organization of single computer containing a control unit, processor unit and a memory unit.
includes many processing units under the supervision of a common control unit
23. A Stack-organised Computer uses instruction of _____.
-
Indirect addressing
Two-addressing
Zero addressing
24.In a program using subroutine call instruction, it is necessary______.
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initialize program counter
Clear the accumulator
Reset the microprocessor
25. Virtual memory consists of _______.
-
Static RAM
Dynamic RAM
Magnetic memory
26. CARRY, in half adder, can be obtained using
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EX-OR gate
AND gate
OR-gate
27. A NAND gate has inputs A and B. It's output is connected to the both of the inputs of another NAND gate. An equivalent gate for these two NAND gates is
-
OR gate
AND gate
NOR gate
28.What characteristic of RAM memory makes it not suitable for permanent storage?
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too slow
unreliable
it is volatile
29. Computers use addressing mode techniques for _____________________.
-
giving programming versatility to the user by providing facilities as pointers to memory counters for loop control
to reduce no. of bits in the field of instruction
specifying rules for modifying or interpreting address field of the instruction
30. Both the arithmetic logic unit (ALU) and control selection of CPU employ special purpose storage locations called
-
decoders
buffers
multiplexer
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