Table of Content (toc)
1. A 4-ary 3-cube hypercube architecture has
-
3 dimensions with 4 nodes along each dimension
4 dimensions what 3 nodes along each dimension
both (a) and (b)
2. Which one of the following Boolean expression represents the SUM output of a HALF-ADDER.
-
A.B
A+B
A’.B’+A.B
3. In a memory-mapped I/O system, which of the following will not be there?
-
LDA
IN
ADD
4. Which of these are examples of 2-dimensional topologies in static networks?
-
Mesh
3CCC networks
Linear array
5. Assembly language ________.
-
uses alphabetic codes in place of binary numbers used in machine language
is the easiest language to write programs
need not be translated into machine language
6. Emitter coupled logic (ECL) belonging to bipolar family is
- The faster logic family and used in high speed application
Most popular family of SSI and MSI chips
Closet and obsolete
7.How is it possible that both programs and date can be stored in the same floppy disk?
-
Programs and data are both software and both can be stored in any memory device
Floppy disks can only store data, not programs
A floppy disk has to be formatted for one or for the other
8. The seek time of a disk is 30 ms. It rotates at the rate of 30 rotations/second. The capacity of each track is 300 words. The access time is approximately
-
62 ms
60 ms
47 ms
9. The information is burnt (prerecorded) into the _____ chip at manufacturing time.
-
PRAM
PROM
ROM
10. What does drive D or E symbolise?
-
Floppy drive
Hard disk
Second floppy drive
11. For two instructions / and / WAR hazard occur, if
-
R(I) D(J)*ø
R(I) R(J) Ø
D(I) R(J) #ø
12. The superscalar issue was first formulated as early as ___. The superscalar processors have to issue multiple instructions per cycle, the first task necessarily is ___.
-
1970, parallel decoding
1975, Pipelines
1980, CISC processors
13. Which operation puts memory address in memory address register and data in DR:
- Memory read
Memory Write
Both
14.The performance of a pipelined processor suffers if
-
the pipeline stages have different delays
Consecutive instructions are dependent on each other
the pipeline stages share hardware resources
15. An interface that provides I/O transfer of data directly to and form the memory unitand peripheral is termed as
-
DDA.
Serial interface.
BR.
16. Bit in short for
-
Binary unit
Binary digit
Digital byte
17. A single bus structure is primarily found in
-
Main frames
High performance machines
Mini and Micro-computers
18. The performance of a memory system is defined by two different measures, the access time and the memory _____ time.
-
response
cycle
access
19. The beginning of the architecture of the Itanium processor took place at ___.
-
Intel
Microsoft
Hewlett-Packard
20. What will be the speed up for a four-stage linear pipeline, when the number of instruction n=64?
-
4.5
7.1
6.5
21. Which Algorithm is better choice for pipelining?
-
Small Algorithm
Hash Algorithm
Merge-Sort Algorithm
22. A memory space used for the temporary storage of data is
-
Buffer
Scratchpad storage
PROM
23. Dynamic pipeline allows
-
Multiples functions to evaluate
only streamline connection
to perform fixed function
24.The correspondence between the main memory blocks and those in the cache is given by
-
Hash function
Mapping function
Locale function
25. The binary equivalent of the decimal number 0.4375 is
-
0.0111
0.1011
0.1100
26. What is à main advantage of classical vector systems (VS) compared with RISC based systems (RS)?
-
VS have significantly higher memory bandwidth than RS
VS have higher clock rate than RS
VS are more parallel than RS
27.The reason for the implementation of the cache memory is
-
To increase the internal memory of the system
The difference in speeds of operation of the processor and memory
To reduce the memory access and cycle time
28. The division of stages of a pipeline into sub-stages is the basis for
-
pipelining
super-pipelining
superscalar
29.Consider the below-mentioned statements with respect to the dataflow graph:
1. Dataflow graph is also called a flow dependency graph.
2. Dataflow graph is asynchronous as the execution of a node starts when matching data is available at a node’s input ports.
State True or False:
-
1- True, 2- True
1- True, 2- False
1- False, 2- True
30. Difference between RISC and CISC is
-
RISC is more complex
CISC is more effective
RISC is better optimizable
Post a Comment
0 Comments