Computer Organization & Architecture MCQ Set - 14 | Computer Organization and Architecture mcq with Answers pdf

 

Table of Content (toc)

1. A 4-ary 3-cube hypercube architecture has

A) 3 dimensions with 4 nodes along each dimension 
B) 4 dimensions what 3 nodes along each dimension
C) both (a) and (b)
D)none of these

ANSWER= (A) 3 dimensions with 4 nodes along each dimension 

 

2. Which one of the following Boolean expression represents the SUM output of a HALF-ADDER.

A) A.B
B) A+B
C)  A’.B’+A.B
D) A.B’+A’.B

ANSWER= (A)  A.B

 

3. In a memory-mapped I/O system, which of the following will not be there?

A) LDA
B) IN
C) ADD
D) OUT

ANSWER= (A) LDA

 

4. Which of these are examples of 2-dimensional topologies in static networks?

A) Mesh
B) 3CCC networks
C) Linear array
D) None of these

ANSWER= (A)  Mesh

 

5. Assembly language ________.

A) uses alphabetic codes in place of binary numbers used in machine language
B) is the easiest language to write programs
C) need not be translated into machine language
D)  None of these

ANSWER= (A)  uses alphabetic codes in place of binary numbers used in machine language

 

6. Emitter coupled logic (ECL) belonging to bipolar family is

A)  The faster logic family and used in high speed application
B) Most popular family of SSI and MSI chips
C) Closet and obsolete
D) New obsolete

ANSWER= (A) The faster logic family and used in high speed application

 

7.How is it possible that both programs and date can be stored in the same floppy disk?

A)  Programs and data are both software and both can be stored in any memory device
B)  Floppy disks can only store data, not programs
C) A floppy disk has to be formatted for one or for the other
D) A floppy disk has two sides, one for data and one for programs

ANSWER= (A) Programs and data are both software and both can be stored in any memory device

 

8. The seek time of a disk is 30 ms. It rotates at the rate of 30 rotations/second. The capacity of each track is 300 words. The access time is approximately

A) 62 ms
B) 60 ms
C)  47 ms
D) none of these

ANSWER= (D) none of these

 

9. The information is burnt (prerecorded) into the _____ chip at manufacturing time.

A) PRAM
B)  PROM
C)  ROM
D) RAM

ANSWER= (C) ROM

 

10. What does drive D or E symbolise?

A) Floppy drive
B) Hard disk
C) Second floppy drive
D) CD-ROM drive

ANSWER= (D) CD-ROM drive

 

11. For two instructions / and / WAR hazard occur, if

A)  R(I) D(J)*ø 
B)  R(I) R(J) Ø
C) D(I) R(J) #ø
D) none of these

ANSWER= (C) D(I) R(J) #ø

 

12. The superscalar issue was first formulated as early as ___. The superscalar processors have to issue multiple instructions per cycle, the first task necessarily is ___.

A) 1970, parallel decoding
B)  1975, Pipelines
C) 1980, CISC processors
D)  None of these

ANSWER= (A)  1970, parallel decoding

 

13. Which operation puts memory address in memory address register and data in DR:

A) Memory read
B) Memory Write
C) Both
D) None

ANSWER= (B) Memory Write

 

14.The performance of a pipelined processor suffers if

A) the pipeline stages have different delays
B)  Consecutive instructions are dependent on each other 
C)  the pipeline stages share hardware resources
D) all of these 

ANSWER= (D) all of these 

 

15. An interface that provides I/O transfer of data directly to and form the memory unitand peripheral is termed as

A)  DDA.
B) Serial interface.
C) BR.
D) DMA.

ANSWER= (D) DMA.

 

16. Bit in short for

A)  Binary unit
B) Binary digit
C) Digital byte
D) Binary system

ANSWER= (B) Binary digit

 

17. A single bus structure is primarily found in

A) Main frames 
B) THigh performance machines
C) Mini and Micro-computers
D) Supercomputers

ANSWER= (C) Mini and Micro-computers

 

18. The performance of a memory system is defined by two different measures, the access time and the memory _____ time.

A) response
B) cycle
C)  access
D) write

ANSWER= (B) cycle

 

19. The beginning of the architecture of the Itanium processor took place at ___.

A)  Intel
B) Microsoft
C) Hewlett-Packard
D) Dell

ANSWER= (C) Hewlett-Packard

 

20. What will be the speed up for a four-stage linear pipeline, when the number of instruction n=64?

A) 4.5 
B) 7.1
C)  6.5
D)  none of these

ANSWER= (D) none of these

 

21. Which Algorithm is better choice for pipelining?

A) Small Algorithm
B) Hash Algorithm
C) Merge-Sort Algorithm
D) Quick-Sort Algorithm

ANSWER= (C) Merge-Sort Algorithm

 

22. A memory space used for the temporary storage of data is

A) Buffer
B) Scratchpad storage
C)  PROM
D)  SAM

ANSWER= (B) Scratchpad storage

 

23. Dynamic pipeline allows

A) Multiples functions to evaluate 
B) only streamline connection
C) to perform fixed function
D) none of these

ANSWER= (A) Multiples functions to evaluate 

 

24.The correspondence between the main memory blocks and those in the cache is given by                    

A) Hash function
B)  Mapping function
C)  Locale function
D) Assign function

ANSWER= (B) Mapping function

 

25. The binary equivalent of the decimal number 0.4375 is

A) 0.0111
B) 0.1011
C) 0.1100
D) 0.1010

ANSWER= (A) 0.0111

 

26. What is à main advantage of classical vector systems (VS) compared with RISC based systems (RS)?

A) VS have significantly higher memory bandwidth than RS
B) VS have higher clock rate than RS 
C) VS are more parallel than RS
D)  None of these 

ANSWER= (A) VS have significantly higher memory bandwidth than RS

 

27.The reason for the implementation of the cache memory is                  

A)To increase the internal memory of the system
B) The difference in speeds of operation of the processor and memory
C) To reduce the memory access and cycle time
D) All of the mentioned

ANSWER= (B)  The difference in speeds of operation of the processor and memory

 

28. The division of stages of a pipeline into sub-stages is the basis for 

A)  pipelining 
B)  super-pipelining 
C) superscalar
D) VLIW processor

ANSWER= (A) pipelining 

 

29.Consider the below-mentioned statements with respect to the dataflow graph:

1. Dataflow graph is also called a flow dependency graph.

2. Dataflow graph is asynchronous as the execution of a node starts when matching data is available at a node’s input ports.

State True or False:

A) 1- True, 2- True
B) 1- True, 2- False
C) 1- False, 2- True
D) 1- False, 2- False

ANSWER= (A)  1- False, 2- True

 

30. Difference between RISC and CISC is

A) RISC is more complex 
B) CISC is more effective
C) RISC is better optimizable
D)  none of these

ANSWER= (A) RISC is more complex 

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