Computer Organization & Architecture MCQ [ Set - 5 ] | Computer Organization and Architecture Mcqs pdf

 Table of Content (toc)

1. Instruction cycle is

A) fetch-decode-execution 
B) decode fetch execution
C) fetch-execution-decode

ANSWER= (A)  fetch-decode-execution 

 

2. In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is             

A) EA = 5+R1
B) EA = R1
C) EA = [R1]
D) EA = 5+[R1]

ANSWER= (D) EA = 5+[R1]

 

3.  The instructions which copy information from one location to another either in theprocessor’s internal register set or in the external main memory are called

A) Data transfer instructions.
B)  Program control instructions.
C) Input-output instructions.
D)  Logical instructions.

ANSWER= (A) Data transfer instructions.

 

4. A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) an address part (allowing for only one address). Each instruction is

A) 6
B) 7
C) 8
D) 9

ANSWER= (C) 8

 

5. In dynamic scheduling, the hardware ___ the instruction execution to reduce stalling of the pipeline.

A) Rearranges
B) Bypasses
C)  Forwards
D) Unhide

ANSWER= (A) Rearranges

 

6.Suppose that a bus has 16 data lines and requires 4 cycles of 250 nsecs each to transfer data. The bandwidth of this bus would be 2 Megabytes/sec. If the cycle time of the bus was reduced to 125 nsecs and the number of cycles required for transfer stayed the same what would the bandwidth of the bus?

A) 1 Megabyte/sec
B) 4 Megabytes/sec
C)  8 Megabytes/sec
D) 2 Megabytes/sec

ANSWER= (D) 2 Megabytes/sec

 

7. Micro instructions are kept in

A) Main memory
B) Control Memory
C) Cache Memory
D) None of these

ANSWER= (A) Types 2nd options

 

8.  At the system level the description of the ___ architecture is based on processor level building blocks.

A) Abstract
B)  Concrete
C) Encapsulated
D)None of the above

ANSWER= (B) Concrete

 

9. Which Logic circuit would you use for addressing memory ?

A) Full adder
B)  Multiplexer
C) Decoder
D) Direct memory access circuit

ANSWER= (C) Decoder

 

10. Booth’s algorithm is used in floating-point

A) addition
B) subtraction
C) multiplication
D) division

ANSWER= (C) multiplication

 

11. Normally digital computers are based on

A)  AND and OR gates
B) NAND and NOR gates
C) NOT gate
D) None of the above

ANSWER= (B) NAND and NOR gates

 

12. Which of the following addressing modes is used in the instruction PUSH B ?

A) Immediate 
B) Register
C)  Direct
D) Register Indirect

ANSWER= (B) Register

 

13. Which of the following addressing modes is used in instruction RAL

A) immediate
B) implied
C) direct
D) register

ANSWER= (B) implied

 

14. Octal number system is

A) A positional system with weights 0 to 9
B) A positional system with weights 0 to 8
C) A positional system with weights 0 to 7
D) A non positional system with weights 0 to 7

ANSWER= (C) A positional system with weights 0 to 7

 

15. Address mode is_______

A) explicitly specified
B) implied by the instruction
C) both a and b
D) neither a nor b

ANSWER= (C) both a and b

 

16. Which of the following affects processing power ?

A) data bus capacity
B)  addressing scheme
C)  clock speed
D) all of the above

ANSWER= (D) all of the above

 

17. Which of the following address modes is used in the instruction 'POP B' ? 

A)  immediate
B)  register
C) direct
D) register indirect

ANSWER= (D) register indirect

 

18. In an instruction the address part points to the address of actual data. The addressing mode is

A)  immediate addressing
B) direct addressing
C)  indirect addressing
D)  none of these

ANSWER= (B) direct addressing

 

19. The main computer that stores files that can be sent to computers that are networked together is

A) Clip art
B) Motherboard
C)  Peripheral
D)  File server

ANSWER= (D)  File server

 

20. A computer uses words of size 32-bit. The instruction

A)  may or may not be one byte length
B) must always be fetched in one cycle with 2 bytes in the cycle 
C)  must always be fetched in two cycles with one byte in each cycle
D)  must be of 2 bytes length

ANSWER= (C) must always be fetched in two cycles with one byte in each cycle

 

21. In daisy-chaining priority method, all the devices that can request an interrupt are connected in

A) parallel
B) serial
C) random
D) none of the above

ANSWER= (B) serial

 

22. The minterms corresponding to decimal number 15 is

A) ABCD
B) (ABCD)’
C) A+B+C+D
D) A’+B’+C’+D’

ANSWER= (D) A’+B’+C’+D’

 

23. To What temporary area can you store and other data, later paste them to another location?

A) The hard disk
B)  CD-ROM
C)  ROM
D) The clipboard

ANSWER= (D) The clipboard

 

24. The CPI value for RISC processor is

A) 1
B) 2
C) 3
D) none of these

ANSWER= (A) 1

 

25. A 32-bit-word computer can access

A) 4
B) 8
C) 16
D) 32

ANSWER= (D) 32

 

26. The 2s compliment form (Use 6 bit word) of the number 1010 is

A) 111100.
B) 110110.
C) 110111.
D) 1011.

ANSWER= (B) 110110.

 

27. In the processor, the address of the next instruction to be executed

A) stack pointer register 
B)  index register 
C) base register
D) program counter

ANSWER= (C) base register

 

28. The BSA instruction is______.

A) Branch and store accumulator
B) Branch and save return address
C) Branch and shift address
D)  Branch and show accumulator

ANSWER= (B) Branch and save return address

 

29. The most common storage device for the personal computer is

A) Hard disk
B)  Zip disk
C)  USB thumb drive
D)  Floppy disk

ANSWER= (A) Hard disk

 

30. A stack-organised computer uses instruction of 

A) Indirect addressing
B) Two addressing
C) Zero addressing
D) Index addressing

ANSWER= (C) Zero addressing

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