Table of Content (toc)
1. The term ‘computer architecture’ was coined in-
-
1972
1978
1964
2. Instruction sets include-
-
Opcode
Addressing modes
Registers
3. Floating point representation is used to store -
-
Boolean values
whole numbers.
real integers
4. In Microsoft Word, which of the following is not a type of text alignment?
-
Midpoint
Left
Right
5. Which of the following are not a machine instructions
-
MOV.
ORG.
END.
6. In signed-magnitude binary division, if the dividend is (11100), and divisor is (10011), then the result is
-
(00100)
(11001)
(10100)
7. The average time required to reach a storage location in memory and obtainits contents is called_____.
-
Latency time.
Access time.
Turnaround time.
8. Which of the following is not true about RAM?
-
Information stored in RAM is gone when you turn the computer off
RAM is volatile
RAM is the same as hard disk storage
9. (-27) io can be represented in a signed magnitude format and in a format is
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111011 & 100100
100100 & 1110111
011011 & 100100
10. The number of select input lines in a 16-to-1 multiplexer is
11. In floating point representation, biased exponent is used to
-
facilitate representation of zero
increase the range of representation
reduce the overhead of comparing the sign bits of exponent in floating arithmetic
12. In Assembly language programming, minimum number of operands required for aninstruction is/are
-
Zero.
One.
Two.
13. The maximum addressing capacity of a micro processor which uses 16 bit database &32 bit address base is
-
64 K.
4 GB.
both (A) & (B) .
14. A three input NOR gate gives logic high output only when_____.
-
one input is high
one input is low
two input are low
15.The circuit converting binary data in to decimal is_____.
-
Encoder
Multiplexer
Decoder
16. Maximum value of a n bit 2's complement number is -
-
2"
2n-1-1
2-1
17. The size gap between main memory & Secondary memory can be reduced by -
-
Cache memory.
memory interleaving
reducing memory size
18. ___ states that “the performance improvement to be gained from using some faster mode of execution is limited by the fraction of the time the faster mode can be used.”
-
Principle of the locality
Hybrid technique
Variable-length technique
19. Dirty bit can be used to represent
-
Noise in data
that the block has been modified in cache
that the memory write operation had been failed
20. The addressing mode used in an instruction of the form ADD X Y, is
-
Absolute
indirect
index
21. Cost per bit is maximum for
-
Cache memory
ROM
RAM
22. The cost-performance ratio is a good indicator of ___ quality for small changes.
-
Relative
Absolute
Absolute relative
23. The access time is maximum in -
-
Cache memory
Register
RAM
24. The algorithm to remove and place new contents into the cache is called
-
Replacement algorithm
Renewal algorithm
Updation
25. The basic circuit ECL supports the
-
NAND logic
NOR logic
EX-OR logic
26. Giga is 2 to the power of
20
27. The speed imbalance between memory access & CPU operation can be reduced by
-
cache memory
memory interleaving
reducing memory size
28. Parallel processing may occur
29.An automatic machine that performs routine seemingly human tasks is
-
AI
PL
Robot
30. TLB is associated with -
-
Cache memory
Virtual memory
Primary memory
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