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Computer Organization & Architecture MCQ [ Set - 12 ] | Computer Organization and Architecture mcq with Answers pdf

computer organization and architecture mcq with answers pdf



 Table of Content (toc)


1.  The term ‘computer architecture’ was coined in-

    1972
    1978
     1964
ANSWER= (C)  1964

 

2. Instruction sets include-

    Opcode
    Addressing modes
    Registers
ANSWER= (D) All of the above

 

3. Floating point representation is used to store -

     Boolean values 
    whole numbers. 
    real integers
ANSWER= (C) real integers

 

4. In Microsoft Word, which of the following is not a type of text alignment?

     Midpoint
     Left
    Right
ANSWER= (A) Midpoint

 

5. Which of the following are not a machine instructions

     MOV.
    ORG.
    END.
ANSWER= (D)  (B) & (C) .

 

6. In signed-magnitude binary division, if the dividend is (11100), and divisor is (10011), then the result is

    (00100)
    (11001)
    (10100) 
ANSWER= (C) (10100) 

 

7. The average time required to reach a storage location in memory and obtainits contents is called_____.

     Latency time.
    Access time.
    Turnaround time.
ANSWER= (B) Access time.

 

8. Which of the following is not true about RAM?

    Information stored in RAM is gone when you turn the computer off
     RAM is volatile
    RAM is the same as hard disk storage
ANSWER= (C) RAM is the same as hard disk storage

 

9. (-27) io can be represented in a signed magnitude format and in a format is

    111011 & 100100 
    100100 & 1110111
    011011 & 100100
ANSWER= (A) 111011 & 100100 

 

10. The number of select input lines in a 16-to-1 multiplexer is





ANSWER= (A) 4

 

11. In floating point representation, biased exponent is used to

     facilitate representation of zero 
    increase the range of representation
     reduce the overhead of comparing the sign bits of exponent in floating arithmetic 
ANSWER= (A)  both (b) & (c)

 

12. In Assembly language programming, minimum number of operands required for aninstruction is/are 

    Zero.
    One.
     Two.
ANSWER= (A) Zero.

 

13. The maximum addressing capacity of a micro processor which uses 16 bit database &32 bit address base is

    64 K.
    4 GB.
    both (A) & (B) .
ANSWER= (B) 4 GB.

 

14.  A three input NOR gate gives logic high output only when_____.

    one input is high
    one input is low
    two input are low
ANSWER= (D) all input are high

 

15.The circuit converting binary data in to decimal is_____.

    Encoder
    Multiplexer
    Decoder
ANSWER= (D) Code converter

 

16. Maximum value of a n bit 2's complement number is -

    2"
    2n-1-1
     2-1
ANSWER= (C)  2-1

 

17.  The size gap between main memory & Secondary memory can be reduced by - 

    Cache memory.
    memory interleaving 
    reducing memory size
ANSWER= (D) Virtual Memory

 

18. ___ states that “the performance improvement to be gained from using some faster mode of execution is limited by the fraction of the time the faster mode can be used.”

     Principle of the locality
     Hybrid technique
     Variable-length technique
ANSWER= (A) Types 2nd options

 

19. Dirty bit can be used to represent

    Noise in data
     that the block has been modified in cache 
    that the memory write operation had been failed

ANSWER= (C) that the memory write operation had been failed

 

20. The addressing mode used in an instruction of the form ADD X Y, is

    Absolute
     indirect
    index
ANSWER= (C) index

 

21. Cost per bit is maximum for

     Cache memory 
    ROM
    RAM
ANSWER= (C) RAM

 

22. The cost-performance ratio is a good indicator of ___ quality for small changes.

    Relative
    Absolute
    Absolute relative
ANSWER= (A) Relative

 

23. The access time is maximum in -

    Cache memory
    Register
    RAM
ANSWER= (D) Hard disk drive

 

24. The algorithm to remove and place new contents into the cache is called                

    Replacement algorithm
    Renewal algorithm
    Updation
ANSWER= (A) Replacement algorithm

 

25. The basic circuit ECL supports the

    NAND logic
    NOR logic
     EX-OR logic
ANSWER= (D) OR-NOR logic

 

26. Giga is 2 to the power of


     20

ANSWER= (B)  20

 

27. The speed imbalance between memory access & CPU operation can be reduced by

    cache memory
    memory interleaving
    reducing memory size  
ANSWER=  both (a) and (b)

 

28. Parallel processing may occur





ANSWER= (C) both[A] and [B]

 

29.An automatic machine that performs routine seemingly human tasks is

     AI
     PL
    Robot
ANSWER= (C) Robot

 

30. TLB is associated with -

    Cache memory 
    Virtual memory 
    Primary memory
ANSWER= (A) Cache memory 




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Computer Organization & Architecture MCQ Set -3(link)












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