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Computer Organization & Architecture MCQ [ Set - 13 ] | mcq on Computer Organisation and Architecture

mcq on Computer Organisation and Architecture

 Table of Content (toc)

1. As per CPU concern Hard disk drive is - 

    type of Memory
     peripheral device 
    both (a) & (b)
ANSWER= (B) peripheral device 


2. Which is the simplest scheme to handle branches?

    Freeze or Flush the pipeline
    Assume each branch as not-taken
    Predict-not-taken or predict-untaken scheme
ANSWER= (A) Freeze or Flush the pipeline


3. The idea of cache memory is based ______.

    on the property of locality of reference
    on the heuristic 90-10 rule
    on the fact that references generally tend to cluster
ANSWER= (A) on the property of locality of reference


4. In a Micro-processor, the address of the next instruction to be executed, is stored in

    Stack pointer
    Address hatch 
     Program counter

ANSWER= (C) Program counter


5.An n-bit microprocessor has_____.

    n-bit program counter
    n-bit address register
    n-bit ALU
ANSWER= (D) n-bit instruction register


6. The least negative value that the product of two 8-bit 2’s complement number can take is


ANSWER= (B) -215


7. Superscalar processors have introduced intricate instruction issue policies, involving advanced techniques such as :

     Shelving, Register naming, Speculative branch processing
     Parallel decoding, Register naming, Shelving
    Design space, Issue Policy, Issue Rate
ANSWER= (A) Shelving, Register naming, Speculative branch processing


8. Which are the operation that a computer performs on data that put in register:

    Register transfer
ANSWER= (D) All of these


9. In microprogramming

ANSWER= (A) Types 2nd options


10. If memory access takes 20 ns with cache and 110 ns with out it, then the ratio ( cache uses a 10 ns memory) is

ANSWER= (B) 90%


11. Which logic gate has the highest speed?



12. CPI stands for-

    Clock cycles per instructions
    Click per instructions
    Cycles per inch
ANSWER= (A) Clock cycles per instructions


13. The expression 'delayed load' is used in context of

    processor-printer communication
    memory-monitor communication
ANSWER= (C) pipelining


14. Which language was devised by Dr. Seymour Cray.



15. AUART is an example of 

     serial asynchronous data transmission ship
    DMA controller
ANSWER= (A) serial asynchronous data transmission ship


16. Logic gates with a set of input and outputs is arrangement of______.

    Computational circuit
    Logic circuit
    Design circuits
ANSWER= (A) Computational circuit


17. _____ are  used to quickly accept, store and transfer data and instructions that are being used immediately by the CPU.

ANSWER= (D) Registers


18. Control program memory can be reduced by

    Horizontal format 
    Vertical format micro-program
    Hardwired control unit
ANSWER= (B) Vertical format micro-program


19.  A JK flip flop has its J input connected to logic level1 and its input to the Q output. A clock pulse is fed to its clock input. The flip – flop will now

    Change its state at each clock pulse
    go to state 1 and stay there
    go to state 0 and stay there
ANSWER= (D) retains its previous state


20. Von Neumann architecture is ______.



21. Pipeline architecture is more suitable for

    RISC architecture
    CISC architecture 
    Hybrid architecture
ANSWER= (A) RISC architecture


22.Floating point representation is used to store ______.

    Boolean values
    whole numbers
     real integers
ANSWER= (C)  real integers


23. Which of the following semiconductor memory, instead of using a flip-flop for the basic memory cell, work by deposition of a charge on a capacitor?

    Dynamic MOS
     Static MOS

ANSWER= (A) Dynamic MOS


24. Overlapped register windows are used to speed-up procedure call and return in

    RISC architectures
     CISC architectures
     both (a) and (b) 
ANSWER= (A) Types 2nd options


25. In pipelining, the CPU executes each instruction in a series of following stages: Instruction Fetching (IF) —–> Instruction Decoding (ID) —–> Instruction Execution (EX) —–>__ and Register Write back (WB).

    Linear pipelines
    Non-linear pipelines
    Structural hazards
ANSWER= (D) Memory access (MEM)


26. The number of cycles required to complete n tasks in a k stage pipeline is

    k + n-1
     nk + 1
ANSWER= (A) k + n-1


27.  In a memory-mapped I/O system, which of the following will not be there?

ANSWER= (A) Types 2nd options


28.  When a machine is pipelined, the ___ execution of instructions requires pipelining of the functional unit.

    Over rode
ANSWER= (C) Overlapped


29.Super scalar instruction issue comprises two major aspects

     Pipelines, Superscalar
    Vector, Sub vector
     Issue Policy, Issue Rate
ANSWER= (C) Issue Policy, Issue Rate


30.  In memory read the operation puts memory address on to a register known as :


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Computer Organization & Architecture MCQ Set -3(link)

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