Table of Content (toc)
1. As per CPU concern Hard disk drive is -
-
type of Memory
peripheral device
both (a) & (b)
2. Which is the simplest scheme to handle branches?
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Freeze or Flush the pipeline
Assume each branch as not-taken
Predict-not-taken or predict-untaken scheme
3. The idea of cache memory is based ______.
-
on the property of locality of reference
on the heuristic 90-10 rule
on the fact that references generally tend to cluster
4. In a Micro-processor, the address of the next instruction to be executed, is stored in
-
Stack pointer
Address hatch
Program counter
5.An n-bit microprocessor has_____.
-
n-bit program counter
n-bit address register
n-bit ALU
6. The least negative value that the product of two 8-bit 2’s complement number can take is
- 214
7. Superscalar processors have introduced intricate instruction issue policies, involving advanced techniques such as :
-
Shelving, Register naming, Speculative branch processing
Parallel decoding, Register naming, Shelving
Design space, Issue Policy, Issue Rate
8. Which are the operation that a computer performs on data that put in register:
-
Register transfer
Arithmetic
Logical
9. In microprogramming
10. If memory access takes 20 ns with cache and 110 ns with out it, then the ratio ( cache uses a 10 ns memory) is
-
93%
90%
88%
11. Which logic gate has the highest speed?
-
DTL
RTL
ECL
12. CPI stands for-
-
Clock cycles per instructions
Click per instructions
Cycles per inch
13. The expression 'delayed load' is used in context of
-
processor-printer communication
memory-monitor communication
pipelining
14. Which language was devised by Dr. Seymour Cray.
-
FORTRAN
LOGO
APL
15. AUART is an example of
-
serial asynchronous data transmission ship
PIO
DMA controller
16. Logic gates with a set of input and outputs is arrangement of______.
-
Computational circuit
Logic circuit
Design circuits
17. _____ are used to quickly accept, store and transfer data and instructions that are being used immediately by the CPU.
-
Graphics
RAMs
Caches
18. Control program memory can be reduced by
-
Horizontal format
Vertical format micro-program
Hardwired control unit
19. A JK flip flop has its J input connected to logic level1 and its input to the Q output. A clock pulse is fed to its clock input. The flip – flop will now
-
Change its state at each clock pulse
go to state 1 and stay there
go to state 0 and stay there
20. Von Neumann architecture is ______.
-
SISD
SIMD
MIMD
21. Pipeline architecture is more suitable for
-
RISC architecture
CISC architecture
Hybrid architecture
22.Floating point representation is used to store ______.
-
Boolean values
whole numbers
real integers
23. Which of the following semiconductor memory, instead of using a flip-flop for the basic memory cell, work by deposition of a charge on a capacitor?
-
Dynamic MOS
Static MOS
CMOS
24. Overlapped register windows are used to speed-up procedure call and return in
-
RISC architectures
CISC architectures
both (a) and (b)
25. In pipelining, the CPU executes each instruction in a series of following stages: Instruction Fetching (IF) —–> Instruction Decoding (ID) —–> Instruction Execution (EX) —–>__ and Register Write back (WB).
-
Linear pipelines
Non-linear pipelines
Structural hazards
26. The number of cycles required to complete n tasks in a k stage pipeline is
-
k + n-1
nk + 1
k
27. In a memory-mapped I/O system, which of the following will not be there?
-
LDA
IN
ADD
28. When a machine is pipelined, the ___ execution of instructions requires pipelining of the functional unit.
-
Overloaded
Over rode
Overlapped
29.Super scalar instruction issue comprises two major aspects
-
Pipelines, Superscalar
Vector, Sub vector
Issue Policy, Issue Rate
30. In memory read the operation puts memory address on to a register known as :
-
PC
ALU
MR
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