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Computer Organization & Architecture MCQ [ Set - 15 ] | Mcq on Computer Organisation and Architecture

Mcq on Computer Organisation and Architecture

 Table of Content (toc)

1. Decimal equivalent of the binary number 101001.1011 is

ANSWER= (C) 41.6875


2. The instruction Processing Unit fetches and decodes ___ and ___ instructions.

    Vector, Sub vector
    Pipelines, parallel task
    Scalar, Vector
ANSWER= (C) Scalar, Vector


3. The addressing mode which makes use of in-direction pointers is              

    Indirect addressing mode
    Index addressing mode
    Relative addressing mode
ANSWER= (A) Indirect addressing mode


4. The advantage of RISC over CISC is that 

    RISC can achieve pipeline segments, requiring just one clock cycle 
    CISC uses many segments in its pipeline with the longest segment requiring two or more clock cycle 
    both (a) & (b)
ANSWER= (D)  none of these


5. A ___ scheduling model is presented for multi-pipeline vector processes.

A long vector task can be partitioned into many ___.

    Parallel task, Sub vectors.
    Sub vectors, parallel task
    Vectors, Pipelining
ANSWER= (A) Parallel task, Sub vectors.


6. _____  addressing mode is most suitable to change the normal sequence of execution of instructions.

    Index with Offset
ANSWER= (A) Relative


7. Which of the following is not RISC architecture characteristic? 

     simplified and unified format of code of instructions.
    no specialized register
    no storage/storage instruction
ANSWER= (C) no storage/storage instruction


8. The enable bit is made _____ after the data to be operated are transferred from main memory.



9. In the year 1834, Babbage attempted to build a digital computer, called ___.

     IAS machine
    Difference engine
    Analytical engine
ANSWER= (C) Analytical engine


10. Which of the following architectures correspond to von-Neumann architecture?



11. One of the chief characteristics of ____ printers is their resolution, how many dots per inch (dpi), they law down.

    Ink jet
ANSWER= (B) Laser


12. Ease-of-use and extensive graphic capabilities are the important characteristics of ___.

    Desktop computers
ANSWER= (B) Desktop computers


13. A pipeline stage

    is sequential circuit
    is combinational circuit
    consists of both sequential and combinational circuits
ANSWER= (C) onsists of both sequential and combinational circuits


14. The ratio which stays constant as performance and cost is increased by equal factors is called as-

    Performance Ratio
    Cost Ratio
    Cost-Performance Ratio
ANSWER= (C) Cost-Performance Ratio


15. Utilization pattern of successive stages of a synchronous pipeline can be specified by

    Truth table 
     Excitation table
    Reservation table 
ANSWER= (A) Reservation table 


16. ___ Complier must be developed to detect :

The concurrency among vector instructions, which can be realized with pipelining.

A ___ compiler would regenerate parallelism lost in the use of sequential languages.

    Intelligent, Vectorizing
    Vectorizing, Intelligent
    Parallel, Pipeline
ANSWER= (A) Intelligent, Vectorizing


17. The effective address of the following instruction is MUL 5(R1,R2).

ANSWER= (C) 5+[R1]+[R2]


18. SPARC stands for

    Scalable Processor Architecture 
    Superscalar Processor A RISC Computer
    Scalable Processor A RISC Computer 
ANSWER= (A)Scalable Processor Architecture 


19. The simplified form of the expression AB+ABC’ is



20. Portability is definitely an issue for which of the following architectures?

    VLIW processor
    Super Scalar processor
    Super pipelined
ANSWER= (B) Super Scalar processor


21. The NAND can function as a NOT gate if (A.B)’=A’+B’

     Inputs are connected together
     One input is set to 0
    One input is set to 1
ANSWER= (D) Both a and c


22. If memory access takes 20 ns with cache and 110 ns without it, then the ratio(cache uses a 10 ns memory) is _____.


ANSWER= (D) 87%


23. Which of the following is not the cause of possible data hazard?



24. _____ stores critical programs such as the program that boots the computer.



25. Which of the following types of instructions are useful in handling sparse vectors or sparse matrices often encountered in practical vector processing application?

    Vector-Scalar instruction
    Masking instruction
    Vector-memory instructions
ANSWER= (B) Masking instruction


26. Define Mapping Process?

    It is a process of transforming data from main memory to cache memory.
    It is a process that signifies the validity of locality of reference.
    It is a process, which translates the main memory address to the cache memory address.
ANSWER= (A) It is a process of transforming data from main memory to cache memory.


27. The vector stride value is required 

     to deal with the length of vectors
     to find the parallelism in vectors
    to access the elements in multi-dimensional vectors
ANSWER= (A)  to deal with the length of vectors


28. There are three classes of Hazards ___, ___ & ___.

     Structural Hazards, Data Hazards, Control hazards.
    Pipeline, System hazards, Data hazards
     Linear, Uniform Linear, Cache
ANSWER= (A) Types 2nd options


29. The addressing mode, where you directly specify the operand value is                

ANSWER= (A) Immediate


30. Basic difference between Vector and Array processors is 

     interconnection network
ANSWER= (A) pipelining

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Computer Organization & Architecture MCQ Set -3(link)

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