Computer Organization & Architecture MCQ [ Set - 15 ] | Mcq on Computer Organisation and Architecture

 Table of Content (toc)

1. Decimal equivalent of the binary number 101001.1011 is

A)  41.0875
B) 40.6875
C) 41.6875
D) 40.0875

ANSWER= (C) 41.6875

 

2. The instruction Processing Unit fetches and decodes ___ and ___ instructions.

A) Vector, Sub vector
B) Pipelines, parallel task
C) Scalar, Vector
D) Pipelines, Scalar

ANSWER= (C) Scalar, Vector

 

3. The addressing mode which makes use of in-direction pointers is              

A) Indirect addressing mode
B) Index addressing mode
C) Relative addressing mode
D) Offset addressing mode

ANSWER= (A) Indirect addressing mode

 

4. The advantage of RISC over CISC is that 

A) RISC can achieve pipeline segments, requiring just one clock cycle 
B) CISC uses many segments in its pipeline with the longest segment requiring two or more clock cycle 
C) both (a) & (b)
D)  none of these

ANSWER= (D)  none of these

 

5. A ___ scheduling model is presented for multi-pipeline vector processes.

A long vector task can be partitioned into many ___.

A) Parallel task, Sub vectors.
B) Sub vectors, parallel task
C) Vectors, Pipelining
D) None of these

ANSWER= (A) Parallel task, Sub vectors.

 

6. _____  addressing mode is most suitable to change the normal sequence of execution of instructions.

A) Relative
B) Indirect
C) Index with Offset
D) Immediate

ANSWER= (A) Relative

 

7. Which of the following is not RISC architecture characteristic? 

A)  simplified and unified format of code of instructions.
B) no specialized register
C) no storage/storage instruction
D) small register file

ANSWER= (C) no storage/storage instruction

 

8. The enable bit is made _____ after the data to be operated are transferred from main memory.

A) 0
B) 1
C) 10
D) 11

ANSWER= (B) 1

 

9. In the year 1834, Babbage attempted to build a digital computer, called ___.

A)  IAS machine
B) Difference engine
C) Analytical engine
D) Pascaline

ANSWER= (C) Analytical engine

 

10. Which of the following architectures correspond to von-Neumann architecture?

A) MISD 
B) MIMD
C)  SISD
D) SIMD

ANSWER= (C) SISD

 

11. One of the chief characteristics of ____ printers is their resolution, how many dots per inch (dpi), they law down.

A) Ink jet
B)  Laser
C) Line
D) Thermal

ANSWER= (B) Laser

 

12. Ease-of-use and extensive graphic capabilities are the important characteristics of ___.

A) Servers
B) Desktop computers
C) Minicomputers
D) Micro-computers

ANSWER= (B) Desktop computers

 

13. A pipeline stage

A) is sequential circuit
B) is combinational circuit
C) consists of both sequential and combinational circuits
D) none of these 

ANSWER= (C) onsists of both sequential and combinational circuits

 

14. The ratio which stays constant as performance and cost is increased by equal factors is called as-

A) Performance Ratio
B) Cost Ratio
C) Cost-Performance Ratio
D)  All of the above

ANSWER= (C) Cost-Performance Ratio

 

15. Utilization pattern of successive stages of a synchronous pipeline can be specified by

A) Truth table 
B)  Excitation table
C) Reservation table 
D) Periodic table

ANSWER= (A) Reservation table 

 

16. ___ Complier must be developed to detect :

The concurrency among vector instructions, which can be realized with pipelining.

A ___ compiler would regenerate parallelism lost in the use of sequential languages.

A) Intelligent, Vectorizing
B) Vectorizing, Intelligent
C) Parallel, Pipeline
D) Cache Memory, data hazards

ANSWER= (A) Intelligent, Vectorizing

 

17. The effective address of the following instruction is MUL 5(R1,R2).

A)  5+R1+R2
B) 5+(R1*R2)
C)  5+[R1]+[R2]
D) 5*([R1]+[R2])

ANSWER= (C) 5+[R1]+[R2]

 

18. SPARC stands for

A) Scalable Processor Architecture 
B) Superscalar Processor A RISC Computer
C) Scalable Processor A RISC Computer 
D) Scalable Pipeline Architecture

ANSWER= (A) Scalable Processor Architecture 

 

19. The simplified form of the expression AB+ABC’ is

A) AB
B) A(B+C)
C) A(B+C)’
D) None of these

ANSWER= (A) AB

 

20. Portability is definitely an issue for which of the following architectures?

A) VLIW processor
B) Super Scalar processor
C) Super pipelined
D)  none of these

ANSWER= (B)  Super Scalar processor

 

21. The NAND can function as a NOT gate if (A.B)’=A’+B’

A)  Inputs are connected together
B)  One input is set to 0
C) One input is set to 1
D) Both a and c

ANSWER= (D) Both a and c

 

22. If memory access takes 20 ns with cache and 110 ns without it, then the ratio(cache uses a 10 ns memory) is _____.

A) 93%
B)  90%
C) 88%
D) 87%

ANSWER= (D) 87%

 

23. Which of the following is not the cause of possible data hazard?

A) RAR 
B) RAW
C) WAR
D) WAW

ANSWER= (A) RAR 

 

24. _____ stores critical programs such as the program that boots the computer.

A)  PRAM
B)  PROM
C)  RAM
D)  ROM

ANSWER= (D)  ROM

 

25. Which of the following types of instructions are useful in handling sparse vectors or sparse matrices often encountered in practical vector processing application?

A) Vector-Scalar instruction
B) Masking instruction
C) Vector-memory instructions
D) None of these

ANSWER= (B) Masking instruction

 

26. Define Mapping Process?

A) It is a process of transforming data from main memory to cache memory.
B) It is a process that signifies the validity of locality of reference.
C) It is a process, which translates the main memory address to the cache memory address.
D)  It is a process of detecting a word in the cache.

ANSWER= (A) It is a process of transforming data from main memory to cache memory.

 

27. The vector stride value is required 

A)  to deal with the length of vectors
B)  to find the parallelism in vectors
C) to access the elements in multi-dimensional vectors
D) to execute vector instruction

ANSWER= (A)  to deal with the length of vectors

 

28. There are three classes of Hazards ___, ___ & ___.

A)  Structural Hazards, Data Hazards, Control hazards.
B) Pipeline, System hazards, Data hazards
C)  Linear, Uniform Linear, Cache
D) Pipeline, Linear, Cache

ANSWER= (A) Types 2nd options

 

29. The addressing mode, where you directly specify the operand value is                

A)  Immediate
B) Direct
C)  Definite
D)  Relative

ANSWER= (A) Immediate

 

30. Basic difference between Vector and Array processors is 

A)  pipelining
B)  interconnection network
C)  register 
D) none of these

ANSWER= (A) pipelining

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