Table of Content (toc)
1. Decimal equivalent of the binary number 101001.1011 is
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41.0875
40.6875
41.6875
2. The instruction Processing Unit fetches and decodes ___ and ___ instructions.
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Vector, Sub vector
Pipelines, parallel task
Scalar, Vector
3. The addressing mode which makes use of in-direction pointers is
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Indirect addressing mode
Index addressing mode
Relative addressing mode
4. The advantage of RISC over CISC is that
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RISC can achieve pipeline segments, requiring just one clock cycle
CISC uses many segments in its pipeline with the longest segment requiring two or more clock cycle
both (a) & (b)
5. A ___ scheduling model is presented for multi-pipeline vector processes.
A long vector task can be partitioned into many ___.
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Parallel task, Sub vectors.
Sub vectors, parallel task
Vectors, Pipelining
6. _____ addressing mode is most suitable to change the normal sequence of execution of instructions.
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Relative
Indirect
Index with Offset
7. Which of the following is not RISC architecture characteristic?
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simplified and unified format of code of instructions.
no specialized register
no storage/storage instruction
8. The enable bit is made _____ after the data to be operated are transferred from main memory.
9. In the year 1834, Babbage attempted to build a digital computer, called ___.
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IAS machine
Difference engine
Analytical engine
10. Which of the following architectures correspond to von-Neumann architecture?
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MISD
MIMD
SISD
11. One of the chief characteristics of ____ printers is their resolution, how many dots per inch (dpi), they law down.
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Ink jet
Laser
Line
12. Ease-of-use and extensive graphic capabilities are the important characteristics of ___.
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Servers
Desktop computers
Minicomputers
13. A pipeline stage
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is sequential circuit
is combinational circuit
consists of both sequential and combinational circuits
14. The ratio which stays constant as performance and cost is increased by equal factors is called as-
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Performance Ratio
Cost Ratio
Cost-Performance Ratio
15. Utilization pattern of successive stages of a synchronous pipeline can be specified by
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Truth table
Excitation table
Reservation table
16. ___ Complier must be developed to detect :
The concurrency among vector instructions, which can be realized with pipelining.
A ___ compiler would regenerate parallelism lost in the use of sequential languages.
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Intelligent, Vectorizing
Vectorizing, Intelligent
Parallel, Pipeline
17. The effective address of the following instruction is MUL 5(R1,R2).
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5+R1+R2
5+(R1*R2)
5+[R1]+[R2]
18. SPARC stands for
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Scalable Processor Architecture
Superscalar Processor A RISC Computer
Scalable Processor A RISC Computer
19. The simplified form of the expression AB+ABC’ is
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AB
A(B+C)
A(B+C)’
20. Portability is definitely an issue for which of the following architectures?
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VLIW processor
Super Scalar processor
Super pipelined
21. The NAND can function as a NOT gate if (A.B)’=A’+B’
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Inputs are connected together
One input is set to 0
One input is set to 1
22. If memory access takes 20 ns with cache and 110 ns without it, then the ratio(cache uses a 10 ns memory) is _____.
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93%
90%
88%
23. Which of the following is not the cause of possible data hazard?
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RAR
RAW
WAR
24. _____ stores critical programs such as the program that boots the computer.
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PRAM
PROM
RAM
25. Which of the following types of instructions are useful in handling sparse vectors or sparse matrices often encountered in practical vector processing application?
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Vector-Scalar instruction
Masking instruction
Vector-memory instructions
26. Define Mapping Process?
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It is a process of transforming data from main memory to cache memory.
It is a process that signifies the validity of locality of reference.
It is a process, which translates the main memory address to the cache memory address.
27. The vector stride value is required
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to deal with the length of vectors
to find the parallelism in vectors
to access the elements in multi-dimensional vectors
28. There are three classes of Hazards ___, ___ & ___.
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Structural Hazards, Data Hazards, Control hazards.
Pipeline, System hazards, Data hazards
Linear, Uniform Linear, Cache
29. The addressing mode, where you directly specify the operand value is
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Immediate
Direct
Definite
30. Basic difference between Vector and Array processors is
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pipelining
interconnection network
register
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